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LVDS IP for SMIC

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Compare 21 LVDS IP for SMIC from 6 vendors (1 - 10)
  • LVDS interfaces
    • Wide operating range
    • High data rates
    • Very flexible programmability
    • Excellent signal integrity
    • TIA/EIA644A LVDS and sub-LVDS compatibility
    • Receiver also compatible with LVPECL
    Block Diagram -- LVDS interfaces
  • Sub-LVDS receiver followed by 1:4 de-serializer
    • Sub-low voltage differential signaling input: VID = 25mV MIN.
    • Converts the subLVDS strobe/data (up to 960 Mbps throughput bandwidth) back into parallel 4 bits of CMOS data/strobe
    • Power-down control function
    • Full industrial operating temperature range -40 ~ +125 °C
  • SMIC 0.13um LVDS Transmitter
    • Supports 18 to 87.5MHz clock
    • 28:4 data channel compression ratio at up to 612.5Mbps per channel data rate
    • No special start-up sequence required between clock/data and PD inputs
    • Supports Spread Spectrum Clocking, up to 100 kHz frequency modulation & deviations of ¡À2.5% center spread or -5% down spread
  • SMIC 0.13um LVDS Receiver
    • Function compatible with the National DS90CF386
    • Converts 4-pair LVDS data stream into parallel 28 bits of CMOS/TTL data
    • Converts 8-pair LVDS data stream into parallel 56 bits of CMOS/TTL data with double channel
    • Wide dot clock range: 25 ~ 170MHz, suitable for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA
  • 650M LVDS transmitter, 5 channel
    • Supports 92MHz clock
    • 35:5 data channel compression at data rate up to 650Mbps per channel
    • Supports single pixel and dual pixel interfaces
    • Converts 70 bits data to 10-pair LVDS data stream
  • LVDS receiver, 650M, 5 channel
    • Function compatible with the National DS90CF386
    • Converts 5-pair LVDS data streams into parallel 35 bits of CMOS/TTL data
    • Converts 10-pair LVDS data streams into parallel 70 bits of CMOS/TTL data with double channel
    • Wide dot clock range: 25-170MHz suited for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA
  • Camera 6/7-mode Combo Receiver - 1G/1.5Gbps
    • The CL12684KM4-8-12-16R3AM6-7ZIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
    • The CL12684KM4-8-12-16R3AM6-7ZIP is designed to support data rate in excess of maximum 1Gbps utilizing sub-LVDS / mini-LVDS / LVDS / HiSPi(SLVS-400, HiVCM) / MIPI-DPHY / CMOS-1.8V / CMOS-3.3V interface specification.
  • LCD Host LVDS Interface, Dual Pixel 20-112Mhz (SVGA/QXGA)
    • 1P6M layout structure based on 0.18um 1P6M 1.8V generic logic process.
    • 3.3V/1.8V ±10% supply voltage, -40/+125°C
    • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
    • Up to 5.38Gbps bandwidth
  • SMIC 0.18um Mini-LVDS Transmitter
    • Process: SMIC 0.18um Logic 1P6M
    • Device list: n18, p18, n33, p33, nnt33, rpposab, ndio33, pdio33
    • Logic input: total 48-bit or 36-bit data input, clock trigger edge selectable
    • Supports 1–port output mode, and 6-pair/3-pair data + SP + clock in this mode
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