IP Catalog > Memory & Libraries IP > I/O Library IP > High-speed IP > LVDS IP > Wide-range LVDS Video Interface

Wide-range LVDS Video Interface

Overview

Flexible video serializer capable of transmitting 18bit, 24bit, and 30bit video data with embedded sync and control over four or five LVDS outputs. Programmable emphasis control on the LVDS outputs ensures compatibility with diverse cable assemblies. The wide-range integer PLL multiplies the pixel clock to generate the serial output clock and has excellent supply noise immunity ensuring the transmitter will perform well in noisy mixed signal SoC environments.

Key Features

  • Wide pixel clock range: 9MHz to 190MHz (VGA to HDTV and QXGA at 60fps) = 60Mb/s to 1.33Gb/s (proven beyond 2Gb/s)
  • Compatible with 18bit, 24bit, and 30bit balanced and unbalanced pixel data
  • 2.5V or 3.3V I/O voltage operation
  • Programmable output levels compatible with EIA/TIA-644 LVDS, subLVDS, and larger amplitude OpenLDI standards
  • Programmable emphasis levels for output drivers supporting transmission over long cables
  • Self-contained: Includes bandgap and PLL
  • LOCK output indicates PLL is locked
  • Serializer reset input to word-align outputs
  • IO library integrated to simplify integration and lower ESD risk
  • Trimmable on-die termination ensures excellent signal integrity
  • Comprehensive power-down control
  • Matching LVDS receiver available

Deliverables

  • GDSII
  • CDL Netlist (MG Calibre Compatible)
  • Functional Verilog Model
  • Liberty timing models (.lib)
  • LEF
  • Application Note with integration and production test guidelines

Technical Specifications

Foundry, Node
TSMC 40LP, TSMC 90G, UMC 28 HLP
Maturity
Silicon Proven
Availability
Available Now
GLOBALFOUNDRIES
Pre-Silicon: 40nm LP
SMIC
Pre-Silicon: 40nm LL
TSMC
In Production: 40nm LP , 90nm G
UMC
Silicon Proven: 28nm HLP
Request Info

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