LVDS interfaces

Overview

LVDS-based IOs

The Bi-directional LVDS is in production from 90nm CMOS to 16/12nm FinFET and taped out in 7nm FinFET. This LVDS I/O is highly programmable and is an excellent IO for FPGA to ASIC conversions.

LVDS-based Interfaces

Based on this versatile LVDS circuit and our robust PLLs and CDR architecture we developed multiple uni-directional and bi-directional parallel source-synchronous interfaces for Chip-chip and Video data transmission. These interfaces can comply with custom chip-chip (or chip-FPGA) requirements or standards including FPDLink, FastLVDS, miniLVDS, FPD Link, Camera Link and OpenLDI. A dynamic phase alignment and robust word alignment architecture enables data rates exceeding 190Mpixels/s (1.34Gb/s in each lane) for FPD-link and up to 3.3Gbps/lane in some cases.

Key Features

Wide operating range
High data rates
Very flexible programmability
Excellent signal integrity
TIA/EIA644A LVDS and sub-LVDS compatibility
Receiver also compatible with LVPECL
Operates over 2Gbps and up to 3Gb/s in some processes
Trimmable on-die termination, can be enabled while Tx is operating for better signal integrity
Independent LVCMOS input and output functions

Benefits

Source-Synchronous receiver compatible with FPD-link, Camera-Link, OpenOLDI, FastLVDS and many others with very wide data rate range and dynamic phase alignment for robust operation.
"Data valid window" measures error rates for each possible phase in each lanes. This one measured at 1.35Gbps with 3% spread spectrum Rx clock shows over 60% opening and validated phase alignment chooses the correct phase.
Eye diagram measured on output of FPD-Link Tx at 1.75Gbps shows excellent signal integrity and plenty of margin to 1.34Gbps maximum specified.

Block Diagram

Technical Specifications

GLOBALFOUNDRIES

Pre-Silicon: 40nm LP

SMIC

Pre-Silicon: 40nm LL

TSMC

In Production: 40nm LP , 90nm G

UMC

Silicon Proven: 28nm HLP

Request Info