800MHz LVDS Cell Set for 180nm

Overview

The OT3910 is a set of cells for implementing 800Mb DDR (400MHz) LVDS IO in 180n CMOS processes.

Includes transmitter and receiver IO's. Also core based bias cell.

An evaluation board and test chip are available. The chip has built in BER testing. Key IO signals are available on coax headers.

Key Features

400MHz (800Mb DDR) operation.
Receive, Transmit and bias cells.
Meets or exceeds the TIA/EIA-644 LVDS standard.
1.8V core voltage.
Integrated 50? termination.
Receive fault detection.
0.3ns differential pulse skew.
1nS receive propagation delay.
Compatible with 75µ wide IOLIB cells.
-40°C to 140°C temperature operation.
Low power dissipation.

Block Diagram

Deliverables

GDS format layout.
Netlist for LVS.
Verilog model.
Metal outline.
Design review spice files.
Timing files.
Integration notes.
Test notes.

Technical Specifications

Foundry, Node

152n, 180n CMOS

Maturity

Silicon

SMIC

Pre-Silicon: 180nm G

TSMC

In Production: 180nm G
Pre-Silicon: 150nm G
Silicon Proven: 180nm G

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