IP Catalog > Foundries > SMIC > Analog IP > Clocking IP

Clocking IP for SMIC

Welcome to the ultimate Clocking IP for SMIC hub! Explore our vast directory of Clocking IP for SMIC
All offers in Clocking IP for SMIC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (98)
Compare 98 Clocking IP for SMIC from 14 vendors (1 - 10)
  • High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
    • Fractional-N digital PLL architecture, using an LC-tank oscillator
    Block Diagram -- High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
  • Low Voltage, Low Power Fractional-N PLLs
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Voltage, Low Power Fractional-N PLLs
  • General Purpose Fractional-N PLLs
    • Low power, suitable for logic clocking applications
    • Extremely small die area, using a ring oscillator
    • Twelve bits fractional resolution
    Block Diagram -- General Purpose Fractional-N PLLs
  • Fractional-N PLLs for Performance Computing
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLLs for Performance Computing
  • PLL system, 2.8 to 3.3 GHz
    • SMIC CMOS 0.18 um technology
    • Wide frequency range (2.8…3.3 GHz)
    • Built-in switched capacitors sections for VCO frequency adjustment
    • Low noise figure
    Block Diagram -- PLL system, 2.8 to 3.3 GHz
  • 7 to 150 MHz digitally controlled oscillator
    • SMIC CMOS 180 nm
    • Wide oscillation frequency adjustment range (7 MHz…150 MHz)
    • No external components required
    • Portable to other technologies (upon request)
    Block Diagram -- 7 to 150 MHz digitally controlled oscillator
  • High Speed PLL
    • Silicon proven in 22, 28, 40, 55, 65, 110, 130, 180nm from SMIC, HHgrace, GlobalFoundries and Samsung.
    • Support integer mode, Fraction mode and Spread-Spectrum mode
    • Input reference range:10MHz~100MHz
    • Core Area:0.0678 mm^2  
    Block Diagram -- High Speed PLL
  • PLL for TSMC 130nm LP
    • Wide range N, M, P integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Comparable frequency range 8MHz – 50MHz.
    • 18pS RMS cycle to cycle jitter at 400MHz.
    • Lock-detect function.
    • Bypass function.
    • Well defined startup behavior.
    • -40°C to 125°C temperature operation.
    • Small cell area: 0.022mm2 in 0.13µ CMOS.
    Block Diagram -- PLL for TSMC 130nm LP
  • General Purpose PLL for TSMC 152nm
    • Wide range M integer divider. (See ot3122 for M, N, and P dividers)
    • 40MHz – 800MHz output frequency range.
    • Comparable frequency range 8MHz – 32MHz.
    • Optional prescaler.
    • 19pS RMS cycle to cycle jitter at 800MHz.
    • Lock-detect function.
    • Bypass function.
    • 20µS well defined fast startup behavior.
    Block Diagram -- General Purpose PLL for TSMC 152nm
  • 4-GHz Jitter-optimized low-power digital PLL
    • - Jitter below 10-ps
    • - Super small: 90 x 90 microns!
    • - Very low power: 15-mW
    • - Broad frequency range: 4-GHz
    Block Diagram -- 4-GHz Jitter-optimized low-power digital PLL
×
Semiconductor IP