IP Catalog > Analog IP > PLL IP > General Purpose PLL IP > General Purpose PLL for TSMC 152nm

General Purpose PLL for TSMC 152nm

Overview

The OT3130 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for the TSMC  0.152µ digital or high voltage CMOS processes. The design features an advanced multi-stage balanced VCO for exceptional cycle to cycle jitter performance, and 20µS start time.

Pricing is $17K for multiuse!

Key Features

  • Wide range M integer divider. (See ot3122 for M, N, and P dividers)
  • 40MHz – 800MHz output frequency range.
  • Comparable frequency range 8MHz – 32MHz.
  • Optional prescaler.
  • 19pS RMS cycle to cycle jitter at 800MHz.
  • Lock-detect function.
  • Bypass function.
  • 20µS well defined fast startup behavior.
  • -40°C to 140°C temperature operation.
  • Available divider selection program.
  • Small cell area: 0.04mm2 in 0.152µ CMOS.
  • 4mW typical power dissipation.
  • 1.8V digital and analog supplies.
  • 0.152µ CMOS process compatibility.
  • Only 1.8V transistors are used in the design.
  • Silicon proven architecture.

Block Diagram

General Purpose PLL for TSMC 152nm Block Diagram

Technical Specifications

Foundry, Node
152n, 180n CMOS
Maturity
Silicon
Availability
Now
SMIC
Silicon Proven: 180nm G
TSMC
In Production: 180nm G , 180nm LP
Pre-Silicon: 150nm G
Silicon Proven: 180nm G , 180nm LP
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