PLL for TSMC 130nm LP

Overview

Key Features

• Wide range N, M, P integer dividers.
• 40MHz – 600MHz output frequency range.
• Comparable frequency range 8MHz – 50MHz.
• 18pS RMS cycle to cycle jitter at 400MHz.
• Lock-detect function.
• Bypass function.
• Well defined startup behavior.
• -40°C to 125°C temperature operation.
• Small cell area: 0.022mm2 in 0.13µ CMOS.
• 2mW typical power dissipation.
• 1.8V digital and analog supplies.
• 0.13µ CMOS process compatibility.
• Only core voltage transistors are used in the design.
• Silicon proven architecture.

Block Diagram

Technical Specifications