Analog IP for SMIC

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Compare 367 Analog IP for SMIC from 20 vendors (1 - 10)
  • GPS/Galileo/GLONASS multisystem single-band receiver
    • SMIC RF CMOS 180 nm technology
    • Single conversion superheterodyne receiver
    Block Diagram -- GPS/Galileo/GLONASS multisystem single-band receiver
  • General Purpose PLL for TSMC 152nm
    • Wide range M integer divider. (See ot3122 for M, N, and P dividers)
    • 40MHz – 800MHz output frequency range.
    • Comparable frequency range 8MHz – 32MHz.
    • Optional prescaler.
    • 19pS RMS cycle to cycle jitter at 800MHz.
    • Lock-detect function.
    • Bypass function.
    • 20µS well defined fast startup behavior.
    Block Diagram -- General Purpose PLL for TSMC 152nm
  • PLL for TSMC 130nm LP
    • Wide range N, M, P integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Comparable frequency range 8MHz – 50MHz.
    • 18pS RMS cycle to cycle jitter at 400MHz.
    • Lock-detect function.
    • Bypass function.
    • Well defined startup behavior.
    • -40°C to 125°C temperature operation.
    • Small cell area: 0.022mm2 in 0.13µ CMOS.
    Block Diagram -- PLL for TSMC 130nm LP
  • 75mA Core Voltage Regulator
    • Input voltage range 3.0V – 3.3V.
    • Output voltage 1.2V or 1.8V ±4%.
    • Output short circuit protection.
    • Bundled with Obsidian 1.2V bandgap reference.
    • Power down/enable input.
    • Fast response to current steps.
    Block Diagram -- 75mA Core Voltage Regulator
  • Power On Reset
    • Input threshold 2VT.
    • Reset and reset bar output logic levels.
    • Minimum 8uS reset pulse for any power rise time.
    • 1µA typical supply current.
    • -40°C to 120°C temperature operation.
    Block Diagram -- Power On Reset
  • TSMC 180nm 5V Bandgap
    • 2.5V-5.5V operation.
    • 3σ 4% untrimmed voltage reference accuracy.
    • 2% variation over -40ºC to 125ºC after trimming.
    • 70dB low frequency PSRR.
    • Trimmed, temperature compensated, 10µA reference current outputs with 3% accuracy.
    • Trimmed IPTAT output currents can be provided.
    • Less than 8µV noise from 0.1Hz to 10KHz.
    Block Diagram -- TSMC 180nm 5V Bandgap
  • Phase-locked loop system 2.8 to 3.3 GHz
    • SMIC CMOS 0.18 um
    • Wide frequency range (2.8…3.3 GHz)
    • Built-in switched capacitors sections for VCO frequency adjustment
    • Low noise figure
    Block Diagram -- Phase-locked loop system 2.8 to 3.3 GHz
  • Temperature sensor
    • SMIC CMOS 0.18 um
    • Built-in 10-bit R-2R DAC
    • Operating temperature range -45 …+100 º C
    • Wide voltage range 2.5 … 3.6 V with own reference voltage former
    Block Diagram -- Temperature sensor
  • 7 to 150 MHz digitally controlled oscillator
    • SMIC CMOS 180 nm
    • Wide oscillation frequency adjustment range (7 MHz…150 MHz)
    • No external components required
    • Portable to other technologies (upon request)
    Block Diagram -- 7 to 150 MHz digitally controlled oscillator
  • LDO voltage regulator (output voltage value 1.8 V, 2.4 V, 2.7 V, 3.0 V)
    • SMIC CMOS 0.18 um
    • High precision stabilization voltage
    • Several operating modes
    • Differential output voltage value (1.8 V, 2.4 V, 2.7 V, 3.0 V)
    Block Diagram -- LDO voltage regulator (output voltage value 1.8 V, 2.4 V, 2.7 V, 3.0 V)
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