IP Catalog > DSP & Math IP > Error Correction/Detection IP

Error Correction/Detection IP

Error Correction/Detection IP cores are specialized hardware modules designed to enhance the reliability and integrity of data transmission and storage in embedded systems. These cores implement advanced error detection and correction algorithms, such as Hamming codes, Reed-Solomon, and BCH, to identify and correct errors in data, ensuring accurate and secure communication. Ideal for applications in memory systems, communication networks, and high-performance computing, Error Correction/Detection IP cores help prevent data corruption, reduce system downtime, and improve overall system performance.

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Search (241)
Compare 241 Error Correction/Detection IP from 39 vendors (1 - 10)
  • DVB-Satellite modulator
    • The CMS0035 DVB-Satellite Modulator is an integrated core featuring our DVB-S/-DSNG modulator (CMS0010) and DVB-S2/-S2X modulator (CMS0025) cores. The CMS0035 core provides all the functionality required to address the requirements of the ETSI forward-link satellite Standards EN 300 421 (DVB-S), EN 301 210 (DSNG), EN 302 307-1 (DVB-S2) and EN 302 307-2 (DVB S2X), with additional support for DVB-S2X VLSNR operation
    • The core can operate in a constant coding-and-modulation (CCM) mode for all Standards and in the enhanced variable-coding-and modulation (VCM) and adaptive-coding-and modulation (ACM) modes provided by DVB-S2 and DVB-S2X.
    Block Diagram -- DVB-Satellite modulator
  • DVB-S2 modulator
    • The CMS0025 DVB-S2/S2X Modulator with integrated LDPC encoder has been designed specifically to address the requirements of the ETSI DVB-S2 forward-link satellite standard (EN 302 307), section-1 together with the section-2 extensions (DVB-S2X), with additional support for DVB-S2X VLSNR operation. The core can operate in CCM and VCM/ACM modes.
    • The core provides all the necessary processing steps to modulate a single transport stream (or baseband frame) into a complex I/Q signal for input to a pair of DACs, or an interpolating DAC device such as the AD9857(or AD9957). Optionally, the output can be selected as an IF to supply a signal DAC.
    Block Diagram -- DVB-S2 modulator
  • Viterbi decoder (burst-mode),
    • The CMS0002 Viterbi Decoder core implements Viterbi’s algorithm for maximum likelihood decoding of non-feedback convolutional codes. Applications include DOCSIS (J.83B), DVB T, 802.11a and 802.16.
    • The basic 1/2 rate convolutional encoder and decoder are shown above. For each input bit, two encoded bits are produced. The rate can be increased to 2/3, 3/4, 5/6, or 7/8 by non transmission (puncture) of certain bits. Punctured codes lose coding gain as the redundant content decreases.
    Block Diagram -- Viterbi decoder (burst-mode),
  • Viterbi decoder (tail-biting)
    • The CMS0008 Viterbi Decoder core implements Viterbi’s algorithm for maximum likelihood decoding of non-feedback convolutional codes.
    • The basic 1/2 rate convolutional encoder and decoder are shown above. For each input bit, two encoded bits are produced. The rate can be increased to 2/3, 3/4, 5/6, or 7/8 by non transmission (puncture) of certain bits. Punctured codes lose coding gain as the redundant content decreases.
    Block Diagram -- Viterbi decoder (tail-biting)
  • Reed Solomon Codec
    • The CMS0013 Reed Solomon Codec provides ultimate flexibility in its operation and build.
    • The design uses the Berlekamp Massey algorithm in order to maximise speed and efficiency.
    Block Diagram -- Reed Solomon Codec
  • Reed Solomon Codec (Errors-only)
    • The CMS0007 Reed Solomon Codec provides ultimate flexibility in its operation and build.
    • The design uses the Berlekamp Massey algorithm in order to maximise speed and efficiency.
    Block Diagram -- Reed Solomon Codec (Errors-only)
  • DVB-Satellite FEC Decoder
    • The CMS0077 Satellite FEC Decoder has been designed specifically to meet the requirements of the DVB-S2 and DVB-S2X advanced wide-band digital satellite standards.
    • The core provides all the necessary processing steps to convert a demodulated complex I/Q signal into a standard TS output stream.
    Block Diagram -- DVB-Satellite FEC Decoder
  • Turbo Intel® FPGA IP
    • Forward-error correction (FEC) channel codes commonly improve the energy efficiency of wireless communication systems
    • Turbo codes are suitable for 3G and 4G mobile communications and satellite communications
    • You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise. The 4G Turbo-V Intel® FPGA IP comprises a downlink and uplink accelerator for vRAN and includes the Turbo Intel® FPGA IP.
    Block Diagram -- Turbo Intel® FPGA IP
  • 5G Polar Intel® FPGA IP
    • The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration into your wireless design
    • Polar codes represent an emerging class of error correction supporting the high throughput requirements for 5G new radio (NR).
    Block Diagram -- 5G Polar Intel® FPGA IP
  • 5G LDPC Intel® FPGA IP
    • Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy channels
    • The 5G LDPC and LDPC-V Intel® FPGA IP implement LDPC codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design.
    • LDPC codes offer better spectral efficiency than Turbo codes and support the high throughput for 5G new radio (NR).
    Block Diagram -- 5G LDPC Intel® FPGA IP
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