DVB-Satellite modulator

Overview

The CMS0035 DVB-Satellite Modulator is an integrated core featuring our DVB-S/-DSNG modulator (CMS0010) and DVB-S2/-S2X modulator (CMS0025) cores. The CMS0035 core provides all the functionality required to address the requirements of the ETSI forward-link satellite Standards EN 300 421 (DVB-S), EN 301 210 (DSNG), EN 302 307-1 (DVB-S2) and EN 302 307-2 (DVB S2X), with additional support for DVB-S2X VLSNR operation. The core can operate in a constant coding-and-modulation (CCM) mode for all Standards and in the enhanced variable-coding-and modulation (VCM) and adaptive-coding-and modulation (ACM) modes provided by DVB-S2 and DVB-S2X.

The core provides all the necessary processing steps to modulate a single transport stream (or baseband frame in the case of DVB-S2/-S2X) into a complex I/Q signal for input to a pair of DACs, or an interpolating DAC device such as the AD9857. Optionally, the output can be selected as an IF to supply a single DAC.

The active DVB-S/-DSNG FEC code-rate is controlled via a control register.

The active DVB-S2/-S2X FEC code-rate and frame size are defined by the mod_cod and type parameters associated with each TS packet (or input-frame) and are controlled through the external mode control ports, or optionally from a control register for CCM applications.

The design has been optimised to provide excellent performance in FPGA devices.

Key Features

  • Fully compliant with ETSI EN 302 307-1 / 302 307-2, ETSI EN 301 210 and ETSI EN 300 421.
  • Variable sample-rate interpolation provides ultra-flexible clocking strategy.
  • Integrated DVB-S channel coder.
  • Optional DVB-DSNG support.
  • Optional DVB-S2X VLSNR support.
  • Optional simultaneous DVB-CID modulation.
  • Support for CCM, VCM and ACM modes.
  • Compatible with Broadcast, DSNG, Interactive and Professional DVB-S2 and DVB-S2X profiles.
  • QPSK, 8-PSK, 16-APSK and 32-APSK supported.
  • 64-APSK, 128-APSK and 256-APSK supported.
  • Short (16kb) and normal (64kb) frames.
  • Frames with/without intra-frame pilots.
  • Automatic dummy-frame insertion.
  • Support for VLSNR frames and encoding.
  • Integrated LDPC channel coder.
  • Configurable for either low-latency or high-throughput encoding.
  • Extension core available for SPI/ASI interface with integrated PCR TS re-stamping.
  • Seamless integration with Altera ASI megacore when using SPI/ASI extension core in broadcast CCM mode.
  • Optional internal IF conversion.
  • Optional noise interference source.
  • AD9857/AD9957 interface and auto-programming support.
  • Modes that are not required may be removed with synthesis options to generate a compact, efficient design.
  • Designed for very efficient FPGA implementation without compromise to the targeting of gate array or standard cell structures.
  • Supplied as a protected bitstream or netlist (Megacore for Altera FPGA targets).

Block Diagram

DVB-Satellite modulator Block Diagram

Deliverables

  • Optimised for ASIC, Xilinx and Altera.
  • Evaluation boards available.

Technical Specifications

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Semiconductor IP