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Forward Error Correction IP

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Search (33)
Compare 33 Forward Error Correction IP from 12 vendors (1 - 10)
  • 2.5 Gbps GPON FEC Codec
    • This high performance core is a full featured Forward Error Correction encoder and decoder, specially designed for high speed optical networks or any other broadband applications.
    • It is fully compliant with the 2.5 Gbps GPON standard (G.984.3) and is available for FPGA or ASIC implementation.
    • The FEC algorithm is based on Reed-Solomon (255,239) code and consists of an encoder and decoder module.
    Block Diagram -- 2.5 Gbps GPON FEC Codec
  • DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
    • Soft-Decision Demapper, Derandomizer, Deinterleaver, Depuncturer, and LDPC Decoder are included
    • Support for 4k and 8K FFT sizes
    • Support for 16-QAM modulation
    Block Diagram -- DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
  • Soft Decision FEC for 200G Optical
    • Baud Rate: ~32 GBaud
    • BPSK, QPSK, and 16-QAM modulation formats
    • FEC Overhead: 7.8% and 20.5% configurable
    Block Diagram -- Soft Decision FEC for 200G Optical
  • Complete FEC Encoder Solution compliant to LTE/ LTE A Specification
    • Controlled selection of Turbo or Convolution path (based on data blocks input or control data input)
    • Rate 1/3 tail biting Convolution encoder
    • Rate 1/3 turbo encoder
    • Rate matching for Turbo coded transport channels
    Block Diagram -- Complete FEC Encoder Solution compliant to LTE/ LTE A Specification
  • 66/2112 Codec for Cyclic Code (2112,2080)
    • Small Size
    • Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
    • 10G/40G/100G Ethernet MAC-friendly interface
    • Practically self-contained: requires only memory for one 2112-bit block in the decoder.
    Block Diagram -- 66/2112 Codec for Cyclic Code (2112,2080)
  • BCH Encoder/Decoder
    • BCH decoder compliant with the DVB-T2/S2 standard.
    • Available for Altera/Xilinx FPGA or ASIC implementation.
    • High speed design.
    • BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
    Block Diagram -- BCH Encoder/Decoder
  • WCDMA Release 9 compliant Viterbi Decoder
    • 3GPP TS 25.212 V 9.5.0 Release 9
    • Supports all block sizes i.e., K=40 - 504.
    • Constraint length of 9
    Block Diagram -- WCDMA Release 9 compliant Viterbi Decoder
  • High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
    • 3GPP LTE/ LTE A compliant
    • Implements decoder for requirements as defined in Section 5.1.3.2 of the specification
    Block Diagram -- High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
  • 4G LTE/LTE-A Turbo Decoder
    • Compliant with 3GPP Release 8 LTE turbo decoding
    • Compliant with 3GPP Release 10 LTE Advanced turbo decoding
    • Support for codeword CRC and up to four transport block CRCs
  • IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder
    • Compliant with IEEE 802.15.3c-2009 standard
    • Suitable for single carrier (SC) mode and high speed interface (HSI) mode.
    • Support for all short LDPC codes (672 bits, code rates 1/2, 5/8, 3/4, 7/8)
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