The patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed. The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance. The decoding IP has several parameters, which can be adjusted at synthesis-time to scale the parallelism, latency and throughput. The decoder list size can be reduced from the typical list 8, in order to best fit the required application.
Functional specifics
| Encoder | Decoder |
|---|---|
| CRC aided SCL encoding | CRC aided SCL decoding |
| Zero padding | Sub block de-interleaving |
| CRC24C attachment | Filler bits insertion/removal |
| CRC scrambling and interleaving | Rate dematching |
| Frozen bit insertion | Channel de-interleaver |
| Sub block interleaving | |
| Rate matching |
Product Codes
| Code | Description | Delivery Type |
|
PD550 |
To enable higher throughput and reduce CPU load. Transport block processing and all code block components are included in the complete Polar 5G NR compliant chain. See Polar decoder chain diagram |
Encrypted RTL or FPGA Netlist |
|
PE550 |
To enable higher throughput and reduce CPU load. Transport block processing and all code block components are included in the complete Polar 5G NR compliant chain. |
Encrypted RTL or FPGA Netlist |
|
PD600 |
Optimized decoder core only for Intel Architecture (IA) and AVX512 co-processor. |
Software binary for IA |
