BCH Encoder/Decoder

Key Features

• BCH decoder compliant with the DVB-T2/S2 standard.
• Available for Altera/Xilinx FPGA or ASIC implementation.
• High speed design.
• BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
• Area and power optimized implementation.
• Compatible flexible and easy integrated with other modules.

Benefits

• Small size (6736 logic slices on Altera Stratix III SL150)
• Fast Design (Max Freq 287 MHz)

Block Diagram

Applications

• DVB-S2/T2 Demodulators

Deliverables

• Synthesizable Verilog
• System Model (Matlab) and documentation
• Verilog Test Benches
• Documentation

Technical Specifications