When Is a Subsystem Not Like an IP?
When is a subsystem not like an IP? I have been asked this question several times and I haven't had a good answer until recently. A change in adoption of one of our tools led me circuitously to a cause, and also to an interesting trend in SoC design. The change is new growth in use of our GenSys tool in the assembly and optimization of subsystems -- particularly ARM and GPU subsystems. Tracing back from that effect to the root cause has taken some detective work. In the process, I gained a better understanding of what makes subsystems more than just "bigger IP."
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related Blogs
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?
- USB4 Sideband Channel Is Not a Side Business
- Tech Note: Use this Flexible and Efficient AC’97 IP Core for Simple Audio Interfaces and Legacy System Upgrades
- Intel's First 14nm Chip NOT an x86 Processor
Latest Blogs
- The Perfect Solution for Local AI
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
- Analog Design and Layout Migration automation in the AI era
- UWB, Digital Keys, and the Quest for Greater Range
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design