VIP Factory: Faster, Better, Cost Effective Verification IPs
December 1, 2014
Today, the EDA industry is emphasizing what is generally known as “Shift Left”. In simple words, this means trying to catch bugs earlier in a chip development cycle. The main reason for this is that the quicker you catch a bug in an ASIC ‘s life cycle, the lesser it costs. With increasing chip complexity, this can save a lot of money, time and effort. Many EDA companies are therefore working on enhancing old tools and building new ones to achieve this. While other approaches will help, the quantum leap in catching bugs faster will be faster and better VIP development. Read on to find how such a "VIP factory" is being developed by Arrow Devices...
Related Semiconductor IP
- Narrow band - IoT Release-14 e-NodeB PHY. (L1) IP
- Narrow band - IoT Release-14 UE PHY. (L1) IP
- Narrow band - IoT Ultra-Low power UE RF Transceiver IP
- Narrow band - IoT Release-14 UE Protocol Stack (L2-L3) Software IP
- Narrow band - IoT Release-14 e-NodeB Protocol Stack (L2-L3) Software IP
Related Blogs
- Synopsys Introduces the Industry's First Verification IPs for Arm AMBA 5 AXI-J and APB-E
- For automotive design, faster is better
- Check Again: Cadence Announces Release of the First PCIe 5.0 VIP - With TripleCheck!
- Industry's First Source Code Test Suite and Verification IP for Arm AMBA ACE5 and AXI5 Enables Early Adopter Success
Latest Blogs
- From guesswork to guidance: Mastering processor co-design with Codasip Exploration Framework
- Enabling AI Innovation at The Far Edge
- Unleashing Leading On-Device AI Performance and Efficiency with New Arm C1 CPU Cluster
- The Perfect Solution for Local AI
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics