Industry's First Source Code Test Suite and Verification IP for Arm AMBA ACE5 and AXI5 Enables Early Adopter Success
Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA CHI Issue B, and verification automation solutions including Auto SoC Testbench Generation and AutoPerformance for AMBA protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of source code test suites and VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications.
Arm just announced the availability of AMBA ACE5 and AXI5 as a part of the AMBA 5 family of protocols, enhancing the standard architecture for next-generation interconnect designs. Synopsys has collaborated with Arm on the creation of this specification and to deliver Synopsys VIP for ACE5 and AXI5 with increased performance for faster verification closure. Synopsys’ VIP for ACE5 and AXI5 is industry’s first source code test suite and VIP for the latest AMBA specifications.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- Synopsys Introduces the Industry's First Verification IP for Arm AMBA 5 CHI-F
- Industry's First Verification IP for Arm AMBA CHI-G
- Synopsys supports launch of Arm AMBA 5 AXI5, ACE5 protocols with 1st source code test suite and VIP
- Synopsys Introduces the Industry's First Verification IPs for Arm AMBA 5 AXI-J and APB-E
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?