Verifying Processor Security, Part 2
This is the second post about Eli Singerman's keynote at the recent Jasper User Group. The first was Formally Verifying Processor Security. In the last couple of years, high-performance processors (not just Intel's) have been shown to be vulnerable to various side-channel attacks. These typically rely on using speculative execution to run code that should not be run, and then, despite the speculative execution being abandoned, some leak of data occurs. The first two such attacks were announced to the public at the start of last year with the names Spectre and Meltdown.
Eli is working on using formal approaches to prove that a future processor is immune to side-channel attacks, and also for analyzing the effects of mitigation on current processors (going back seven years). This is not just hardware that needs to be analyzed, but core firmware (in the processor itself) and other firmware (in devices like cameras and accelerators).
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related Blogs
- Formally Verifying Processor Security
- Upcoming IoT Security Legislation: Vulnerability Disclosure - Part 2
- EDA Carnivores, part 2: Apache acquires Sequence Design
- ST-Ericsson (Part 2): Diverse Offering
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms