Verifying and Debugging Storage Protocols: SATA
September 14, 2015
In this video, Synopsys Applications Consultant, Vijay Akkaraju, describes the evolving Storage ecosystem, the challenges of verifying storage protocol based system, and how Synopsys’ SATA Verification IP can support you in verifying and debugging your designs efficiently and effectively.
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related Blogs
- Formally verifying protocols
- Interface Protocols, USB3, PCI Express, MIPI, SATA... the winners and losers in 2012
- Scaling Out Deep Learning (DL) Inference and Training: Addressing Bottlenecks with Storage, Networking with RISC-V CPUs
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
Latest Blogs
- CAVP-Validated Post-Quantum Cryptography
- The role of AI processor architecture in power consumption efficiency
- Evaluating the Side Channel Security of Post-Quantum Hardware IP
- A Golden Source As The Single Source Of Truth In HSI
- ONFI 5.2: What’s new in Open NAND Flash Interface's latest 5.2 standard