Formally verifying protocols
November 16, 2011
I attended much of the Jasper users' group a week ago. There were several interesting presentations that I can't just blog about because companies are shy, and some that would only be of interest if you were a user of Jasper's products on a daily basis.
But for me the most interesting presentations were several on an area that I didn't realize this sort of formal verification was being used for. The big driver is that modern multi-core processors now require much more sophisticated cache control than before. ARM in particular has created some quite sophisticated protocols under the AMBA4 umbrella that they announced at DAC.
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Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related Blogs
- Addressing Heterogenous Verification and Validation Requirements for Compute Express Link (CXL) Designs Using Synopsys Protocol Continuum
- Standing the Test of Time: How Advanced Protocol Verification Creates Bulletproof SoC Designs
- How to Speed Up Simulation Coverage Closure with Formal Verification Tools
- Raising RISC-V processor quality with formal verification