Formally verifying protocols
I attended much of the Jasper users' group a week ago. There were several interesting presentations that I can't just blog about because companies are shy, and some that would only be of interest if you were a user of Jasper's products on a daily basis.
But for me the most interesting presentations were several on an area that I didn't realize this sort of formal verification was being used for. The big driver is that modern multi-core processors now require much more sophisticated cache control than before. ARM in particular has created some quite sophisticated protocols under the AMBA4 umbrella that they announced at DAC.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
Related Blogs
- Addressing Heterogenous Verification and Validation Requirements for Compute Express Link (CXL) Designs Using Synopsys Protocol Continuum
- Standing the Test of Time: How Advanced Protocol Verification Creates Bulletproof SoC Designs
- How to Speed Up Simulation Coverage Closure with Formal Verification Tools
- Raising RISC-V processor quality with formal verification
Latest Blogs
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success
- Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach
- UEC-CBFC: Credit-Based Flow Control for Next-Gen Ethernet in AI and HPC