Synopsys Advances Die‑to‑Die Connectivity with 64G UCIe IP Tape‑Out

By Synopsys, Inc.

April 2, 2026

Introduction

Synopsys has successfully completed tape-out of its 64Gbps Universal Chiplet Interconnect Express (UCIe) IP on 2-nm process technology, marking a significant milestone in enabling the next wave of high-performance, energy-efficient multi-die designs. As AI, HPC, and advanced networking workloads continue to drive unprecedented bandwidth and integration requirements, this latest UCIe IP provides designers with a scalable, production-ready interconnect optimized for demanding short-reach die-to-die links.

Key Features of Synopsys 64G UCIe IP

Built on Synopsys’ proven UCIe expertise, the 64G UCIe IP maintains industry-leading energy efficiency. The solution helps designers maximize performance per watt, an increasingly critical metric for AI accelerators and multi-die designs deployed at scale. The IP supports dense configurations, delivering multi-terabit-per-second bandwidth per millimeter to address the I/O bottlenecks of advanced multi-die designs.

The 64G UCIe IP features a lightweight implementation optimized for captive systems, enabling designers to integrate high-bandwidth die-to-die connectivity without unnecessary overhead. A modular architecture allows adaptation to specific system requirements, giving designers the flexibility to balance bandwidth, power, and area across a wide range of applications. Support for streaming protocols further simplifies integration into data-intensive designs that demand low-latency throughput.

Reliability and robustness are central to the design. The IP includes extensive testability along with bring-up and debug capabilities to accelerate system validation and reduce time to production. Optional error detection and correction mechanisms, supporting UCIe CRC as well as liteFEC, provide additional protection for high-speed links, helping ensure data integrity across advanced package and interconnect environments.

Comprehensive Solution for Advanced and Standard Packaging

To support broad adoption across today’s packaging ecosystems, the 64G UCIe IP is designed to work across standard and advanced package technologies.

The solution is delivered as a complete UCIe offering, spanning controller, PHY, adapter layers, verification IP, emulation support, and package-level SI/PI considerations. By addressing the full die-to-die interconnect stack, Synopsys helps customers reduce integration risk and accelerate time-to-market for complex multi-die systems.

Explore UCIe IP:

• UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
• UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
• UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)

Why It Matters

As multi-die architectures become the foundation for scaling performance beyond monolithic SoCs, die-to-die interconnects increasingly determine system-level power, bandwidth, and time-to-market. By delivering 64Gbps-per-pin performance with industry-leading energy efficiency in a production-ready UCIe implementation, Synopsys enables architects to push bandwidth density while keeping power and integration risk under control. This allows design teams to more confidently adopt multi-die design approaches for AI, High-Performance Computing (HPC), and data-intensive applications, accelerating innovation without compromising reliability or efficiency.

With the tape-out of its 64G UCIe IP, Synopsys continues to advance the state of the art in die-to-die connectivity, empowering customers to scale bandwidth, improve energy efficiency, and confidently deliver next-generation multi-die designs for the most demanding AI and HPC workloads.

Learn how Synopsys accelerates multi-die innovatio