Keeping Up with UCIe 1.1 Verification Using Synopsys VIP for UCIe
Ever since UCIe™ (Universal Chiplet Interconnect Express™) consortium was formed and version 1.0 of the UCIe specification was released, the chiplet/die-to-die ecosystem has been frenzied. IP architects and developers have their task cut-out for them – to come up with a robust design and implementation that benefits from the heterogenous system without compromising their power, performance, and area (PPA) goals. System architects and designers are busy putting the technology in their next generation SoCs. Verification teams are running against time to create test and coverage plans based on the integrated logic before they receive disintegrated chip RTL.
Let’s review what we have seen in the first revision of the specification.
- Multi-layer protocol: application specific protocol layer, die-to-die adapter and physical layer
- Signalling interface between different layers
- FDI (flit-aware die-to-die interface) between protocol layer and die-to-die adapter
- RDI (raw die-to-die interface) between die-to-die adapter and physical layer
- Physical link interface between two dies
- Separate mainband and sideband interface at all the layers
- Native specifications support for CXL, PCIe and streaming protocol
- Single and multi-module in physical layer interface
While the first revision focused on features for signaling and chiplet architecture, version 1.1 addresses compliance and interoperability to support multi-vendor heterogenous systems.
Let’s demystify what’s happening in newly released specification.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related Blogs
- Industry's First Verification IP for Arm AMBA CHI-G
- Verifying CXL 3.1 Designs with Synopsys Verification IP
- Industry's First Verification IP for PCIe 7.0
- Synopsys Introduces Industry's First 40G UCIe IP Solution to Power High-Performance Multi-Die Designs
Latest Blogs
- Shaping the Future of Semiconductor Design Through Collaboration: Synopsys Wins Multiple TSMC OIP Partner of the Year Awards
- Pushing the Boundaries of Memory: What’s New with Weebit and AI
- Root of Trust: A Security Essential for Cyber Defense
- Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update
- An Introduction to AMBA CHI Chip-to-Chip (C2C) Protocol