Tag it! Your customer will love using IP compliant with TSMC9000 IP Tag specification
We have seen last week in a first post how crucial was the IP qualification process (TSMC 9000) to increase the probability of successfully Tape Out a chip. Being able to discriminate between dangerous and safe IP is the first step of TSMC 9000 Quality process, IP tagging is the complementary step, almost as essential as the first one. That’s why, for every IP or Library going through TSMC 9000, an unique IP tag is created and inserted into its GDSII stream for identification.
The IP Tag allows carrying the IP vendor information and IP denomination, and also all the quality information and production status of the specific IP or Library.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
- Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
Related Blogs
- Specification Ambiguities of MIPI UniPro v1.41 clarified in MIPI UniPro v1.6
- New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions
- New AMBA 5 ACE/AXI Specification: More About Atomic Transactions
- New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP
Latest Blogs
- A Comparison on Different AMBA 5 CHI Verification IPs
- Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
- Accelerating Development Cycles and Scalable, High-Performance On-Device AI with New Arm Lumex CSS Platform
- Desktop-Quality Ray-Traced Gaming and Intelligent AI Performance on Mobile with New Arm Mali G1-Ultra GPU
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet