New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions
The recent update of the AMBA® 5 ACE/AXI specification introduces a number of significant performance improvements which help to align the protocol to the more recent AMBA® 5 CHI (Coherent Hub Interface) specification. One of the most prominent features is introduction of atomic transactions. Before we take a close look at this new class of transactions, let’s look back in time.
Previous generations of AMBA ACE/AXI protocols have included support of exclusive accesses which relied on the semaphore-type operations. A typical exclusive access had the following steps:
To read the full article, click here
Related Semiconductor IP
- AMBA 5 CHI Verification IP
- AMBA 5 CHI Verification IP
- AMBA 5 AHB Bus Verification IP
- AMBA 5 AHB Verification IP
- AMBA 5 CHI Synthesizable Transactor
Related Blogs
- New AMBA 5 ACE/AXI Specification: More About Atomic Transactions
- New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP
- Arm AMBA 5 AHB5: Accelerating the Embedded and IoT World
- Synopsys Introduces the Industry's First Verification IP for Arm AMBA 5 CHI-F
Latest Blogs
- A Low-Leakage Digital Foundation for SkyWater 90nm SoCs: Introducing Certus’ Standard Cell Library
- FPGAs vs. eFPGAs: Understanding the Key Differences
- UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
- RT-Europa: The Foundation for RISC-V Automotive Real-Time Computing
- Arm Flexible Access broadens its scope to help more companies build silicon faster