New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions
February 2, 2018
The recent update of the AMBA® 5 ACE/AXI specification introduces a number of significant performance improvements which help to align the protocol to the more recent AMBA® 5 CHI (Coherent Hub Interface) specification. One of the most prominent features is introduction of atomic transactions. Before we take a close look at this new class of transactions, let’s look back in time.
Previous generations of AMBA ACE/AXI protocols have included support of exclusive accesses which relied on the semaphore-type operations. A typical exclusive access had the following steps:
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Related Semiconductor IP
- AMBA 5 CHI Verification IP
- AMBA 5 AHB Bus Verification IP
- AMBA 5 AHB Verification IP
- AMBA 5 CHI Synthesizable Transactor
- AMBA 5 CHI Assertion IP
Related Blogs
- New AMBA 5 ACE/AXI Specification: More About Atomic Transactions
- New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP
- Why do I need an AMBA 5 CHI Memory Controller?
- Introducing new AMBA 5 CHI protocol enhancements