New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP
April 4, 2018
As discussed in the previous installments of the blog, the recent update of the AMBA® 5 ACE/AXI specification introduced several performance improvement features which align the AMBA5 ACE/AXI protocol with AMBA 5 CHI (Coherent Hub Interface) specification. Among them is the new class of atomic transactions, discussed in-depth previously.
Another new transaction class includes the new cache stash transactions which install a cache line in the cache of another component in the system, moving it closer to the point of use, thus improving the overall system performance.
To read the full article, click here
Related Semiconductor IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
Related Blogs
- New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions
- New AMBA 5 ACE/AXI Specification: More About Atomic Transactions
- Arm AMBA 5 AHB5: Accelerating the Embedded and IoT World
- Synopsys Introduces the Industry's First Verification IP for Arm AMBA 5 CHI-F
Latest Blogs
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing
- Post-quantum security in platform management: PQShield is ready for SPDM 1.4