New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP
April 4, 2018
As discussed in the previous installments of the blog, the recent update of the AMBA® 5 ACE/AXI specification introduced several performance improvement features which align the AMBA5 ACE/AXI protocol with AMBA 5 CHI (Coherent Hub Interface) specification. Among them is the new class of atomic transactions, discussed in-depth previously.
Another new transaction class includes the new cache stash transactions which install a cache line in the cache of another component in the system, moving it closer to the point of use, thus improving the overall system performance.
To read the full article, click here
Related Semiconductor IP
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
- I2C and SPI Master/Slave Controller
- AHB/AXI4-Lite to AXI4-Stream Bridge
Related Blogs
- New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions
- New AMBA 5 ACE/AXI Specification: More About Atomic Transactions
- Arm AMBA 5 AHB5: Accelerating the Embedded and IoT World
- Synopsys supports launch of Arm AMBA 5 AXI5, ACE5 protocols with 1st source code test suite and VIP