The Truth of TSMC 28nm Yield!
April 16, 2012
As I write this I sit heavyhearted in the EVA executive lounge returning from my 69th trip to Taiwan. I go every month or so, you do the math. This trip was very disappointing as I can now confirm that just about everything you have read about TSMC 28nm yield is absolutely MANURE!
Please let me apologize to the hard working people of TSMC and the leading edge fabless semiconductor engineers that are bringing 28nm silicon to our hands and homes this year. On behalf of all of the people around the world who Blog and Tweet ignorant things, they know not what they type, I’m very very sorry.
To read the full article, click here
Related Semiconductor IP
- 10mA, Capless High PSRR LDO Regulator for RF and Analog Applications in TSMC 28nm
- 30mA, Capless High PSRR LDO Regulator for RF and Analog Applications in TSMC 28nm
- 40mA, Capless High PSRR LDO Regulator for RF and Analog Applications in TSMC 28nm
- Low-power, high-speed 11-bit, 8 GSPS Analog to Digital Converter IP block - TSMC 28nm HPC+ process
- 18-bit Sigma Delta Stereo Audio Analog-to-Digital Converter IP in TSMC 28nm
Related Blogs
- TSMC Gets 28nm Yield Up Over 80%
- Moore's Law and 28nm Yield
- TSMC on 40nm and 28nm yield issues
- TSMC 28nm Yield Explained!
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview