Subsystem IP, myth or reality?
December 7, 2012
I have participated to a panel during IP-SoC, I must say that “Subsystem IP, myth or Reality” was a great moment. The panel was a mix of mid-size IP vendor (CAST, Sonics), one large EDA (Martin Lund from Cadence), Semiwiki blogger and one large IDM (Peter Hirt from STM) who has very well represented the customer side. And, to make the panel even more efficient, the audience was great, with Joachim Kunkel from Synopsys and Philippe Quiniot, STM Group VP, IP Sourcing & Strategy, or Marc Miller, VP Marketing for Tabula, to name a few very active participants.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- NavIC LDPC Decoder
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
Related Blogs
- Co-design - Myth or Reality?
- Dis-ARMing the data center - Separating myth from reality
- Empowering AI-Enabled Systems with MIPI C/D-PHY Combo IP: The Complete Audio-Visual Subsystem and AI
- Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem
Latest Blogs
- Evolution of CXL PBR Switch in the CXL Fabric
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success