SiFive RISC-V Proven in 5nm Silicon
OpenFive Tapes Out SoC for Advanced AI/HPC Solutions on TSMC 5nm Technology
Today, I am pleased to see OpenFive, a SiFive business unit that is the leading provider of customizable, silicon-focused solutions with differentiated IP, is continuing to make progress with AI design solutions with the creation of a reference design chiplet architecture using OpenFive Die-to-Die interface, OpenFive HBM3 IP subsystem, and SiFive 7-Series processor IP, for 2.5D-based SoCs. More details on the full announcement can be found on OpenFive’s announcement here, but today I want to call out the SiFive milestone of our first RISC-V processor core in 5nm.
The SiFive RISC-V-based processor portfolio is the broadest in the industry, from our upcoming SiFive Intelligence processor cores featuring RISC-V vector capabilities to area-optimized real-time cores. SiFive believes that it takes more than great processor IP to be successful in these markets by offering class-leading advanced trace and debug IP enabled by SiFive Insight. SiFive Insight is delivered pre-integrated with SiFive processor cores and gives customers the tools they need to develop sophisticated applications and is well supported by leading industry tool vendors, IAR Systems, Lauterbach, and SEGGER. Uniquely, SiFive Insight is compatible with Arm® Coresight™ to simplify the use of RISC-V in mixed-ISA environments.
To read the full article, click here
Related Semiconductor IP
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- All-In-One RISC-V NPU
Related Blogs
- The Heart of RISC-V Development is Unmatched
- SiFive collaborates with new Intel Foundry Services to enable innovative new RISC-V computing platforms
- Delivering on the Promise of Industry-Leading RISC-V Processors
- RISC-V Chiplets, Disaggregated Die, and Tiles
Latest Blogs
- Cadence Powers AI Infra Summit '25: Memory, Interconnect, and Interface Focus
- Integrating TDD Into the Product Development Lifecycle
- The Hidden Threat in Analog IC Migration: Why Electromigration rules can make or break your next tapeout
- MIPI CCI over I3C: Faster Camera Control for SoC Architects
- aTENNuate: Real-Time Audio Denoising