Samsung Foundry Accelerates Billion-Gate Low-Power Signoff with Synopsys VC LP
For today’s mobile and high-performance systems, low-power design is essential. Such designs are more sustainable, translate to longer battery life, create better seamless consumer experiences, and reduce energy costs. All these benefits aside, reducing power consumption is a challenging task for chip designers and verification/RTL engineers. Next-generation SoCs are expected to be 10x larger, and low-power signoff for some designs can take as long as a couple of days. Clearly, an advanced low-power verification solution is needed to help engineers validate complex low-power structures within a reasonable turnaround time.
One such solution is Synopsys VC LP™ Advanced static low-power verification solution, which has successfully passed Samsung Foundry’s certification process. As a static checking product, VC LP Advanced technology effectively addresses the complexity of validating low-power designs, streamlining and expediting the debugging process.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Blogs
- How to Achieve Faster Signoff of Billion-Gate, Low-Power SoCs
- NeuReality Accelerates 7nm AI Chip Tape-Out with Cloud-Based Emulation
- Reducing Errors and Iterations with an Enhanced Timing Constraints Signoff Flow
- Samsung is NOT a Foundry!
Latest Blogs
- UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
- RT-Europa: The Foundation for RISC-V Automotive Real-Time Computing
- Arm Flexible Access broadens its scope to help more companies build silicon faster
- Embedded Security explained: IPsec and IKEv2 for embedded Systems
- Deploying StrongSwan on an Embedded FPGA Platform, IPsec/IKEv2 on Arty Z7 with PetaLinux and PQC