Samsung Foundry Accelerates Billion-Gate Low-Power Signoff with Synopsys VC LP
For today’s mobile and high-performance systems, low-power design is essential. Such designs are more sustainable, translate to longer battery life, create better seamless consumer experiences, and reduce energy costs. All these benefits aside, reducing power consumption is a challenging task for chip designers and verification/RTL engineers. Next-generation SoCs are expected to be 10x larger, and low-power signoff for some designs can take as long as a couple of days. Clearly, an advanced low-power verification solution is needed to help engineers validate complex low-power structures within a reasonable turnaround time.
One such solution is Synopsys VC LP™ Advanced static low-power verification solution, which has successfully passed Samsung Foundry’s certification process. As a static checking product, VC LP Advanced technology effectively addresses the complexity of validating low-power designs, streamlining and expediting the debugging process.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- MIPI D-PHY1.2 CSI/DSI TX and RX
- Low-Power ISP
- eMMC/SD/SDIO Combo IP
- DP/eDP
Related Blogs
- How to Achieve Faster Signoff of Billion-Gate, Low-Power SoCs
- Samsung Foundry and Synopsys Accelerate Multi-Die System Design
- Running X-Propagation with Low-Power Simulation
- NeuReality Accelerates 7nm AI Chip Tape-Out with Cloud-Based Emulation
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms