Samsung Foundry Accelerates Billion-Gate Low-Power Signoff with Synopsys VC LP
For today’s mobile and high-performance systems, low-power design is essential. Such designs are more sustainable, translate to longer battery life, create better seamless consumer experiences, and reduce energy costs. All these benefits aside, reducing power consumption is a challenging task for chip designers and verification/RTL engineers. Next-generation SoCs are expected to be 10x larger, and low-power signoff for some designs can take as long as a couple of days. Clearly, an advanced low-power verification solution is needed to help engineers validate complex low-power structures within a reasonable turnaround time.
One such solution is Synopsys VC LP™ Advanced static low-power verification solution, which has successfully passed Samsung Foundry’s certification process. As a static checking product, VC LP Advanced technology effectively addresses the complexity of validating low-power designs, streamlining and expediting the debugging process.
To read the full article, click here
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- Parameterizable compact BCH codec
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
Related Blogs
- How to Achieve Faster Signoff of Billion-Gate, Low-Power SoCs
- NeuReality Accelerates 7nm AI Chip Tape-Out with Cloud-Based Emulation
- Reducing Errors and Iterations with an Enhanced Timing Constraints Signoff Flow
- Samsung is NOT a Foundry!
Latest Blogs
- Rivian’s autonomy breakthrough built with Arm: the compute foundation for the rise of physical AI
- AV1 Image File Format Specification Gets an Upgrade with AVIF v1.2.0
- Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES
- Integrating Post-Quantum Cryptography (PQC) on Arty-Z7
- UA Link PCS customizations from 800GBASE-R Ethernet PCS Clause 172