Rambus Offers MIPI Controller Support for Xilinx LogiCORE D-PHY with 2.5 Gbps/Lane
The Rambus’ CSI-2 Tx/Rx Controller Cores and DSI-2 Host/Peripheral Cores with support of up to 2.5 Gbps/lane is available with the LogiCORE D-PHY on Kintex and Zynq Ultrascale+ devices. With the highest D-PHY lane rates available in any FPGA, the Rambus MIPI Controllers are high performance, high quality, easy-to-use CSI-2 and DSI-2 Cores which are being used in more leading FPGA-based applications.
“We are pleased to see the widespread adoption of 2.5 Gbps/lane LogiCORE D-PHY with CSI-2/DSI-2 Controller Cores in the FPGA market,” said Joe Rodriguez, Product Marketing Manager, Rambus. The solution is validated for use with the LogiCORE D-PHY and fully integrated into Xilinx Vivado design implementation flow. More details on Rambus MIPI controllers are available here.
Related Semiconductor IP
- I3C Master / Slave Controller - MIPI Basic v1.0
- MIPI Controller IP, CSI-2 Transmitter, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP
- MIPI Controller IP, DSI Peripheral, Soft IP
- MIPI Controller IP, DSI Host, Soft IP
- MIPI Controller IP, CSI-2 Receiver, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP
Related Blogs
- Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI-SIG Conferences
- Integrated MIPI Display IP Solution Delivers Performance for New Use Cases
- MIPI Alliance Releases Enhanced I3C Host Controller Interface
- PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview