See Demonstration Video of PCIe 4.0 PHY IP in TSMC 16FF+
March 1, 2016
Did you miss DesignCon this year? If so, you also missed the demonstration of our PCIe 4.0 PHY silicon. You can read more about the demo here.
The IP is implemented in TSMC 16FF+, and is in use by several customers to enable the next generation green datacenter. The underlying SerDes operates from 1.25Gbps to 16Gbps, and was shown supporting the PCIe 4.0 protocol. You can read more about the IP here.
And you can watch a video of the demo here.
Related Semiconductor IP
- PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation
- PCIe 4.0 PHY, TSMC 16FFPGL x4, North/South (vertical) poly orientation
- PCIe 4.0 PHY, TSMC 16FFPGL x16, North/South (vertical) poly orientation
- PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
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- Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process
- Flow Control Credit Updates in PCIe 6.1 ECN
- Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
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