HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF
High-performance and high-speed memory design characterized by low-power operation are requirements for today’s leading edge electronics. Cadence is a leader in providing advanced process node, low-power memory IP. Recent news with Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and HiSilicon Technologies Co. Ltd highlights our collaboration to meet the needs of industry leaders in this area. This is the first customer to license the Cadence® Denali® DDR4 PHY IP, implemented on the TSMC 16nm FinFET process.
To read the full article, click here
Related Semiconductor IP
- DDR4 PHY
- DDR4 PHY - TSMC N7
- DDR4 PHY - GLOBALFOUNDRIES 12nm
- TSMC CLN7FFLVT 7nm DDR4 PHY - 4266Mbps
- TSMC CLN7FF 7nm DDR4 PHY - 4266Mbps
Related Blogs
- Next-Generation DDR4 and LPDDR4 IP in TSMC 16FF+ Enable 200Gb+ Data Transfers for Mobile, Cloud, and IoT Platforms
- See Demonstration Video of PCIe 4.0 PHY IP in TSMC 16FF+
- Who needs DDR4 PHY running at 2667 Mbps?
- Cadence Ports LPDDR4/DDR4 Combo PHY to TSMC 28HPC to Serve Rapid Adoption in Consumer Products
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power