HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF
February 3, 2015
High-performance and high-speed memory design characterized by low-power operation are requirements for today’s leading edge electronics. Cadence is a leader in providing advanced process node, low-power memory IP. Recent news with Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and HiSilicon Technologies Co. Ltd highlights our collaboration to meet the needs of industry leaders in this area. This is the first customer to license the Cadence® Denali® DDR4 PHY IP, implemented on the TSMC 16nm FinFET process.
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