Living on the Smart Edge: reflecting on a great year at Ceva
As we bid farewell to 2023, it is with great satisfaction that we look at our remarkable achievements. This year has been a transformative one for Ceva, marked by the beginning of a new era for Ceva and its partners – the era of the smart edge, with focus on IP innovation and growth.
Refocus on innovative IP for the Smart Edge
We define the Smart Edge as consisting of all devices that are close either to the user – like wearables and cars, the sensor – like smart home and smart cities, or the edge of the network – such as access points, satellites, and base stations, as illustrated in below diagram. Smart edge devices can be found in all markets which Ceva focuses on, in consumer IoT, mobile, automotive, infrastructure, industrial, and personal computing. As a result, we have redefined our mission statement to capture this firm commitment – to be the partner of choice for transformative IP solutions for the Smart Edge.
As part of this transformation, Ceva has expanded its IP portfolio solutions to offer a comprehensive silicon IP portfolio including platforms for 5G cellular, Wi-Fi, Bluetooth, UWB, and NB-IoT, processors for digital signal processing (DSP), TinyML processing, and neural processing (NPU), as well as embedded application software IP for ambient sensing and immersive audio that makes it easy for customers to deploy application ready end user solutions that utilize audio, voice and sensors.
To read the full article, click here
Related Semiconductor IP
- xSPI Multiple Bus Memory Controller
- MIPI CSI-2 IP
- PCIe Gen 7 Verification IP
- WIFI 2.4G/5G Low Power Wakeup Radio IP
- Radar IP
Related Blogs
- A Focus on Mission-Critical Defense Solutions at GOMACTech
- World IP Day: A Time to Reflect on the Value of Semiconductor IP
- Morello Program one year on: A step closer to securing our digital future
- A Primer on Multi-Die Systems
Latest Blogs
- The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
- Unlock early software development for custom RISC-V designs with faster simulation
- HBM4 Boosts Memory Performance for AI Training
- Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
- Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA