How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?
The chip design industry is going through exciting times. Process nodes with smaller geometries have always enticed chip manufacturers and OEMs, as it helps integrate more functionality over SoC. This reduction in the process nodes has been predicted by Moore's law and achieved through scaling rules as per Dennard's law.
Moore's law held for decades, but with the effective upper bound of clock frequencies, quantum tunneling and interconnects limitations, etc., it is on the deathbed. In addition, as shown in the figure, maximum clock frequency has decreased, and even single-thread performance improvements have slowed considerably.
To read the full article, click here
Related Semiconductor IP
- Very Low Latency BCH Codec
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
- AXI-S Protocol Layer for UCIe
- HBM4E Controller IP
Related Blogs
- How Physical AI Is Redefining the Automotive Industry
- The Link Between Cars and Smartphones: How MIPI Protocol IP Is Helping the Auto Industry Shape Its Future
- A Trillion-Dollar Industry: How AI Is Reinventing EDA and Semiconductors
- How the SiFive HiFive Premier P550 is Accelerating Linux Ecosystem Adoption
Latest Blogs
- Embedded Security explained: Post-Quantum Cryptography (PQC) for embedded Systems
- Accreditation Without Compromise: Making eFPGA Assurable for Decades
- Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
- World First: Synopsys MACsec IP Receives ISO/PAS 8800 Certification for Automotive and Physical AI Security
- Last-level cache has become a critical SoC design element