DDR4 PHY
Overview
The DDR4 multiPHY is a complete mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a System-On-a-Chip (SOC) design targeted to a specific fabrication process. The DDR4 multiPHY supports a range of SDRAM speeds, from DDR3-400 through DDR4-2400. Targeted toward supporting, x8 and x16 SDRAM components, DDR4 multiPHY supports interfaces of varying widths, from a minimum of 8 bits wide, in 8-bit increments. Delivered to customers as hardened IP components —Address/Command (AC), Data (DAT), PLL, and SSTL I/O Library —implementations of the DDR4 multiPHY are compatible with JEDEC DDR SDRAMs, helping ensure customer success.
Key Features
- ? DDR4, LPDDR3, LPDDR2, DDR3, DDR3L, and DDR3U operation
- ?1.2V DDR4 SDRAMs operating at data rates up to 2400Mbps
- ?1.2V LPDDR2 SDRAMs operating at data rates up to 1066Mbps
- ?1.35V DDR3L SDRAMs operating at data rates up to 1866Mbps
- ?1.25V DDR3U SDRAMs operating at data rates up to 1600Mbps
- ? Scalable performance from 0 MBps LPDDR2/LPDDR3 through DDR4-2400
- ? Maximum controller clock frequency of 600 MHz resulting in maximum SDRAM data rate of 2400Mbps
- ? Data path width scales in 8-bit increments, with allowances for partially-populated upper-most byte enables any DRAM width
- ? Delivery of product as a hardened macrocell allows precise control of timing critical delay and skew paths
- ? Includes PLL and Digital Delay Lines necessary to meet timing specifications
- ? Multiple (4) memory rank support
Deliverables
- We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.
Technical Specifications
Foundry, Node
TSMC,40
Maturity
Silicon Proven
Availability
Immediate
TSMC
Silicon Proven:
40nm
G