Innovation in Design Rules Verification Keeps Scaling on Track
There is an interesting dynamic that occurs in the semiconductor industry when we talk about process evolution, roadmaps and generally attempt to peer into the future. First, we routinely scare ourselves by declaring that scaling can’t continue and that Moore’s Law is dead (a declaration that has happened more often than the famously exaggerated rumors of Mark Twain’s death). Then, we unfailingly impress ourselves by coming up with solutions and workarounds to the show-stopping challenge of the day. Indeed, there has been a remarkable and consistent track record of innovation to keep things on track, even when it appears the end is surely upon us.
But this time we are really serious – at 20nm, the end is near! Ok, maybe not THE end, but for sure there are some obvious things that need to change if we are to keep our record of continuous technical conquest intact. And, as with most things in this era, collaboration is the key.
To read the full article, click here
Related Semiconductor IP
- eFPGA on GlobalFoundries GF12LP
- ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
- MIPI C/D Combo PHY RX - GlobalFoundries 22FDX
- Power On Reset, 200uA Delay Time - GlobalFoundries 180nm
- GF 0.13um BCD LIN PHY IP, >20Kbps - GlobalFoundries 130nm
Related Blogs
- Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple
- 4 Ways that Digital Techniques Can Speed Up Memory Design and Verification
- DDR5 DIMM Design and Verification Considerations
- Understanding UCIe Design Verification Topologies
Latest Blogs
- How Arasan’s SoundWire PHY Can Elevate Your Next Audio SoC
- Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos
- Introducing the Akeana 1000 Series Processors
- How fast a GPU do you need for your user interface?
- PCIe 6.x and 112 Gbps Ethernet: Synopsys and TeraSignal Achieve Optical Interconnect Breakthroughs