Understanding UCIe Design Verification Topologies
UCIe or Unified Chiplet Interconnect Express is the fastest growing chiplet interconnect standard that enables a future where a catalog of chiplets will be available to mix and match based on the chip designs in the sphere of AI, network computing, etc. It is a multi-layer, multi-protocol with well-defined die-to-die interfaces.
Its stack is broken down into three major layers, namely:
- Protocol Layer
- Die-to-Die Adapter Layer and
- Physical Layer
Each of the above-mentioned layers has a wide array of capabilities, such as multi-protocol support (CXL, PCIe, and Streaming), varying interface widths and data rates, protocol multiplexing, and packaging options, to name a few. This gives options to design simple as well as the most sophisticated chiplets based on the end application. As an example, one version of Physical Layer Chiplet design could have Standard Packaging support and another version could support Advanced Packaging with increased link width.
To read the full article, click here
Related Semiconductor IP
- ISO/IEC 7816 Verification IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
Related Blogs
- Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple
- 4 Ways that Digital Techniques Can Speed Up Memory Design and Verification
- DDR5 DIMM Design and Verification Considerations
- Low-Power IC Design: What Is Required for Verification and Debug?
Latest Blogs
- A Comparison on Different AMBA 5 CHI Verification IPs
- Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
- Accelerating Development Cycles and Scalable, High-Performance On-Device AI with New Arm Lumex CSS Platform
- Desktop-Quality Ray-Traced Gaming and Intelligent AI Performance on Mobile with New Arm Mali G1-Ultra GPU
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet