DDR5 Is on Our Doorstep
October 15, 2018
The talk of the town in the DRAM market (well, apart from its growth in the last couple of years) is DDR5. You might assume from the talk that JEDEC has finalized the standard, but it is actually technically still in development. I believe that the final standard is still expected before the end of the year.
At TSMC's OIP Ecosystem Forum, Cadence's Marc Greenberg and Micron's Ryan Baxter presented on DDR5 Challenges and Solutions. The two companies decided not to wait for the final ink to dry on the standard since engineering takes too long, so they agreed on a detailed spec that was close to what they expected the final standard to be.
Related Semiconductor IP
- DDR5 PHY - TSMC N5
- DDR5 PHY - TSMC N4P
- DDR5 PHY - TSMC N3P
- DDR5 MRDIMM2 PHY - TSMC N3P
- DDR5 PHY - TSMC N3E
Related Blogs
- AMI for DDR5 Made Easy
- DDR5 IP Test Chip Operates with Micron Prototype DRAM at 4400 MT/s
- How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a Preliminary Version of the DDR5 Standard
- DDR5 - Off and Running
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?