DDR5 Is on Our Doorstep
October 15, 2018
The talk of the town in the DRAM market (well, apart from its growth in the last couple of years) is DDR5. You might assume from the talk that JEDEC has finalized the standard, but it is actually technically still in development. I believe that the final standard is still expected before the end of the year.
At TSMC's OIP Ecosystem Forum, Cadence's Marc Greenberg and Micron's Ryan Baxter presented on DDR5 Challenges and Solutions. The two companies decided not to wait for the final ink to dry on the standard since engineering takes too long, so they agreed on a detailed spec that was close to what they expected the final standard to be.
To read the full article, click here
Related Semiconductor IP
- DDR5 Controller - Ensures high-speed, efficient operation and compatibility of memory controllers
- Simulation VIP for DDR5 DIMM
- Simulation VIP for DDR5
- DDR5 IP solution
- DDR5 RDIMM Verification IP
Related Blogs
- AMI for DDR5 Made Easy
- DDR5 IP Test Chip Operates with Micron Prototype DRAM at 4400 MT/s
- How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a Preliminary Version of the DDR5 Standard
- DDR5 - Off and Running
Latest Blogs
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
- ReRAM-Powered Edge AI: A Game-Changer for Energy Efficiency, Cost, and Security
- Ceva-XC21 and Ceva-XC23 DSPs: Advancing Wireless and Edge AI Processing
- Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process
- Empowering your Embedded AI with 22FDX+