DDR5 IP Test Chip Operates with Micron Prototype DRAM at 4400 MT/s
The DDR5 standard has not been finalized by JEDEC, and they are very strict about not allowing anyone to claim DDR5 compatibility until the standard is complete. That is expected sometime this summer. However, getting designs into silicon can't wait until the standard is final before getting started. In principle, anything could change in the standard at any time until it is released, but everyone knows that the basic parameters are not going to change at this late date. Almost exactly two years ago, Mellanox's Gilad Shainer said to me that "interoperability is the only way to prove standards compliance." He was talking about PCIe 4.0, a standard that hadn't been completed when we talked. But the same idea applies to next-generation DRAM.
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