DDR5 MRDIMM PHY and Controller

PHY

• Includes DDR5 training with write-leveling and data-eye training, and I/O pads with impedance calibration logic and data retention capability
• Programmable per-bit (PVT compensated) deskew on read and write data paths
• RX and TX equalization for heavily loaded systems
• Microcontroller-based PHY-independent advanced training that provides flexibility
• Low latency for data-intensive applications
• Signal integrity, board, and package design guidelines

Controller

• QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces
• Memory controller interface complies with DFI standards up to version 5.1

• Scalable: The flexible floorplan design options enable easy integration into advanced SoCs, allowing for scalable solutions that can grow with your needs.
• High Performance: Industry-first Cadence DDR5 12.8Gbps MRDIMM Gen2 PHY and controller doubles the performance of DDR5 DRAM.
• Enhanced Memory Bandwidth: Addresses the need to accommodate AI processing demands in enterprise and data center applications.
• Power and Performance Tuning: The architecture allows fine-tuning of power and performance based on individual application requirements.