How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a Preliminary Version of the DDR5 Standard
We’re thrilled to have announced our prototype 7nm DDR5 IP silicon based on a preliminary version of the DDR5 standard at this week's TSMC Technology Symposium. This has been a huge amount of work from the DDR teams at Cadence and sets a landmark for the adoption of a new memory standard in the industry.
This has been quite an experience for us, starting in 2017 when we developed the prototype DDR5 PHY and DDR5 Controller IP, basing it on preliminary ballots and discussion on the DDR5 standard which even today has not yet been released. Fortunately, we have a lot of silicon ‘firsts’ and one of the hallmarks of our IP is its adaptability, we were able to put enough flexibility into the design to ensure first-time silicon success
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