Mobiveil's UMMC LPDDR3/2 Controller is a highly flexible and configurable design. It is targeted for high bandwidth access and low power consumption such as next-generation mobile, networking and consumer applications. The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities.
UMMC LPDDR3/2 Controller is part of Mobiveil's Storage and Memory controller family of IP solutions which also includes UMMC DDR5/4/3, NVM Express Controller (UNEX), Enterprise Flash Controller (EFC), and LDPC Encoder/Decoder IP cores.
The controller's configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible AXI System interface makes it easy to be integrated into wide range of applications. UMMC LPDDR3/2 controller leverages Mobiveil's years of experience in HyperTransport, PCI, PCIe and RapidIO technologies and in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and inter-operability.
Universal Multiport Memory Controller - LPDDR 3/2 Controller
Overview
Key Features
- Compliant with AXI V4.0 specification
- Compliant with DFI 3.1 specification
- Compliant with JEDEC LPDDR2 and LPDDR3 standards
- Support for 8, 16, 32 SDRAM bus width, for a total memory data path width up to 64 bits
- Supports chip select interleaving
- Supports single and multi-port host buses AMBA 4 AXI up to 32 ports
Benefits
- Support for up to four ranks (chip selects) and 4/8 banks per rank (chip select)
- Supports MC Clock to PHY Clock ratio in Full/Half/Quarter rate mode
- Supports Auto-refresh, per bank refresh, self-refresh, power-down, and deep power down modes
- Maximizes bus efficiency through look-Ahead command processing, bank level parallelism and intelligent request scheduling
- Built-in asynchronous interface support for DRAM frequencies that are not equal to the AXI frequency
- Separate write and read queues
- The AXI ID signals support out-of-order transactions
- Design Attributes
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Software control for key features
Block Diagram
Deliverables
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- Documentation
- Design Guide
- Verification Guide
- Synthesis Guide
Technical Specifications
Foundry, Node
ANY
Maturity
Silver