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LPDDR4 IP

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Search (202)
Compare 202 IP from 21 vendors (1 - 10)
  • Simulation VIP for LPDDR4
    • Speed (Mt/s)
    • 2133MHz (4266MT/s)
    • Device Density
    • Supports a wide range of device densities from 4Gb to 32Gb
    Block Diagram -- Simulation VIP for LPDDR4
  • LPDDR4 Synthesizable Transactor
    • Supports 100% of LPDDR4 protocol standard JESD209-4,JESD209-4A,JESD209-4B,JESD209-4C,JESD209-4D,JESD209-4X and JESD209-4Y (proposed)
    • Supports all the LPDDR4 commands as per the specs
    • Supports memory densities upto 32GB
    • Supports device types X8 and X16
    Block Diagram -- LPDDR4 Synthesizable Transactor
  • LPDDR4 DFI Synthesizable Transactor
    • Compliant with DFI version 4.0 or 5.0 Specifications.
    • Supports LPDDR4 devices compliant with JEDEC LPDDR4 SDRAM Standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4X and LPDDR4Y (Proposed).
    • Supports for Read data-eye training
    • Supports for Read gate training
    Block Diagram -- LPDDR4 DFI Synthesizable Transactor
  • LPDDR4 Memory Model
    • Supports LPDDR4 memory devices from all leading vendors.
    • Supports 100% of LPDDR4 protocol standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C, JESD209-4D, JESD209-4X and LPDDR4Y (Proposed).
    • Supports all the LPDDR4 commands as per the specs.
    • Supports up to 32 GB device density.
    Block Diagram -- LPDDR4 Memory Model
  • LPDDR4 DFI Verification IP
    • Compliant with DFI version 4.0 or 5.0 Specifications.
    • Supports LPDDR4 devices compliant with JEDEC LPDDR4 SDRAM Standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4X and LPDDR4Y (Proposed).
    • Supports for Read data-eye training
    • Supports for Read gate training
    Block Diagram -- LPDDR4 DFI Verification IP
  • LPDDR4 Controller IIP
    • Supports LPDDR4 protocol standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C, JESD209-4X and JESD209-4Y (Proposed) Specification.
    • Compliant with DFI version 4.0 or 5.0 Specification.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
    Block Diagram -- LPDDR4 Controller IIP
  • LPDDR4 Assertion IP
    • Specification Compliance
    • Supports 100% of LPDDR4 protocol standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4D, JESD209-4X and JESD209-4Y(Proposed).
    • Supports all the LPDDR4 commands as per the specs.
    • Quickly validates the implementation of the LPDDR4 standard JESD209-4,JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4D, JESD209-4X and JESD209-4Y (Proposed).
    Block Diagram -- LPDDR4 Assertion IP
  • LPDDR4 DFI Assertion IP
    • Specification Compliance
    • Compliant with DFI version 4.0 or 5.0 Specifications.
    • Supports LPDDR4 devices compliant with JEDEC LPDDR4 SDRAM Standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4X and LPDDR4Y (Proposed).
    • Supports for Read data-eye training
    Block Diagram -- LPDDR4 DFI Assertion IP
  • LPDDR4 multiPHY V2 - UMC 28HPC+18
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - UMC 28HPC+18
  • LPDDR4 multiPHY V2 - TSMC28HPC+18
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - TSMC28HPC+18
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