Cadence Memory IP for LPDDR4 Certified in TSMC 16FFC
April 23, 2019
Last week, Cadence announced the certification of its LPDDR4 IP in TSMC's 16nm automotive process. The opening paragraph of the press release actually says:
"Cadence Design Systems, Inc today announced that the Cadence LPDDR4/4X memory IP subsystem, utilizing the TSMC 16nm FinFET Compact (16FFC) automotive process technology, has achieved ISO 26262 ASIL C certification from SGS-TÜV Saar. The certification confirms that the Cadence IP is complete and ready for use by customers creating advanced systems-on-chip (SoCs) for ADAS and L3/L4 autonomous driving applications."
That's a lot of jargon in a few lines. Let me unpack it.
To read the full article, click here
Related Semiconductor IP
- Simulation VIP for LPDDR4
- LPDDR4 Synthesizable Transactor
- LPDDR4 DFI Synthesizable Transactor
- LPDDR4 Memory Model
- LPDDR4 DFI Verification IP
Related Blogs
- CXL 3.1: What's Next for CXL-based Memory in the Data Center
- GDDR7: The Ideal Memory Solution in AI Inference
- Flow Control Credit Updates in PCIe 6.1 ECN
- Partial Header Encryption in Integrity and Data Encryption for PCIe
Latest Blogs
- The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
- Unlock early software development for custom RISC-V designs with faster simulation
- HBM4 Boosts Memory Performance for AI Training
- Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
- Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA