DAC 2022 - Is it too risky not to adopt RISC-V?
I was fortunate enough to attend the 59th Design Automation Conference (DAC) in San Francisco last week. Aside from the Covid closure in 2020 I’ve been going to DAC since 1995. Many people, including me, arrived to the San Francisco with a bit of trepidation. After all, 58th DAC had low attendance and it was only ~7 months ago. What was the DAC 2022 conference going to be like? How would Covid affect things? Would international travelers come to San Francisco?
Frankly, I was impressed! Yes, the exhibit hall is smaller than it used to be. Yes, the attendance is not what it was in the 2000’s… and yes, there were times where it was quite slow on the exhibit floor. At the end of the day the many international travellers did show up and the conference and exhibits were quite well attended. At Codasip we met with customers and prospects from all over the world — Korea, Japan, Europe, the US, and more.
Related Semiconductor IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32 Bit - Embedded RISC-V Processor Core
Related Blogs
- No Need to Reinvent the Wheel: How Easy It Is to Build with RISC-V
- Embedded World 2022 - the RISC-V genie is out of the bottle
- What is Spatial Audio and What Does it Have To Do With Binaural Audio?
- How Arm is making it easier to build platforms that support Confidential Computing
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?