DAC 2022 - Is it too risky not to adopt RISC-V?
I was fortunate enough to attend the 59th Design Automation Conference (DAC) in San Francisco last week. Aside from the Covid closure in 2020 I’ve been going to DAC since 1995. Many people, including me, arrived to the San Francisco with a bit of trepidation. After all, 58th DAC had low attendance and it was only ~7 months ago. What was the DAC 2022 conference going to be like? How would Covid affect things? Would international travelers come to San Francisco?
Frankly, I was impressed! Yes, the exhibit hall is smaller than it used to be. Yes, the attendance is not what it was in the 2000’s… and yes, there were times where it was quite slow on the exhibit floor. At the end of the day the many international travellers did show up and the conference and exhibits were quite well attended. At Codasip we met with customers and prospects from all over the world — Korea, Japan, Europe, the US, and more.
To read the full article, click here
Related Semiconductor IP
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- All-In-One RISC-V NPU
Related Blogs
- What is the Right Metric to Understand 5G Processing Throughput? Well, it’s not Peak Speed....
- Embedded World 2022 - the RISC-V genie is out of the bottle
- What It Will Take to Build a Resilient Automotive Compute Ecosystem
- Breaking the Silence: What Is SoundWire‑I3S and Why It Matters
Latest Blogs
- Shaping the Future of Semiconductor Design Through Collaboration: Synopsys Wins Multiple TSMC OIP Partner of the Year Awards
- Pushing the Boundaries of Memory: What’s New with Weebit and AI
- Root of Trust: A Security Essential for Cyber Defense
- Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update
- An Introduction to AMBA CHI Chip-to-Chip (C2C) Protocol