CXL Controller with Zero Latency IDE: You Can't Do Better Than Zero
October 7, 2021
The virtuous cycle of data holds that as volume increases, the value increases. More volume requires faster processing and faster links. More value demands that computing and connecting be secure. That’s why the Compute Express Link™ (CXL) standard specifies that its speedy links be protected by Integrity and Data Encryption (IDE). But if the implementation of IDE introduces latency overhead, then you’re operating at cross purposes where performance is sacrificed for security.
To read the full article, click here
Related Semiconductor IP
- CXL Controller
- CXL CONTROLLER IIP
- PCIe 6.0 Retimer Controller with CXL Support
- PCIe 7.0 Retimer Controller with CXL Support
- Compute Express Link (CXL) 1.1/2.0/3.0 Controller
Related Blogs
- Automating Data Coherency and Performance Testing of High-Speed SoCs with CXL Interfaces
- How the CXL Standard Improves Latency in High-Performance Computing
- How CXL Is Improving Latency in High-Performance Computing
- Verification of Integrity and Data Encryption (IDE) for CXL Devices