Compute Express Link (CXL) 1.1/2.0/3.0 Controller
Overview
The KappaCORE-64 from Alphawave Semi is a CXL™ Controller IP that implements the latest CXL 3.0 spec, which is backward compatible with CXL 2.0 and CXL 1.1 specs. This controller forms a complete CXL solution, when integrated with Alphawave Semi’s PipeCORE-64 PCIe PHY IP.
Key Features
- Implements CXL 3.0 Specification at 64 GT/s
- Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
- Designed for easy integration with PipeCORE™ PCIe® PHY IP
- Key IP features configurable to optimize IP for exact application requirements
Benefits
- Customer Configurable
- The KappaCORE CXL Controller IP is customer configurable and supports CXL 3.0 Specification with the PipeCORE PCIe and CXL PHY Interface utilizing the latest Intel PIPE 6.x specification and supports up to x16 lane widths.
- The CXL IP is built on top of the PCIe Controller IP for the CXL.io path and adds additional support for CXL.mem and CXL.cache traffic.
- Configurability
- KappaCORE-64 can be configured to support two key modes, Device Dual Mode (“Root Port” or “Endpoint”), Switch Dual Mode (“Switch Downstream Port” or “Switch Upstream Port”). This allows users to use the IP in a wide variety of PCIe applications.
- Verification
- The IP has been verified against leading CXL VIP and available compliance test suite. This IP is proven in silicon using a Alphawave PHY IP on a Test chip. The controller IP has also been verified in emulation as well as on an FPGA using Xilinx PHY interoperating with an Intel CXL Sapphire Rapids Motherboard.
- Customizability
- To easily optimize the CXL IP for the exact application requirements, the IP comes with an easy-to-use, graphical IP Configuration wizard that allows users to enable, disable, or tune features in the IP, or to add or remove optional ECNs (Engineering Change Note). The IP supports multiple data path widths designed for optimal area when used for narrower lane widths.
Block Diagram
