Cadence Implementation Flow for an ARM Cortex-A73 at 10nm
October 10, 2016
Increasingly, taking an appropriate ARM® processor has become the standard way to pipe-clean a digital flow in a new process. ARM processors are widely used and are available at various levels of complexity. For 10nm (what TSMC calls N10), Cadence and ARM worked together to implement a Cortex®-A73 core, which is ARM's highest performance mobile processor. At TSMC's OIP Symposium recently, a joint presentation by Paddy Mamtora of Cadence and Shawn Hung of ARM went into the details.
There were several goals:
- Ensure ARM's next-generation CPU is optimized for advanced process
- Ensure EDA tools and ecosystem are ready for lead partners
- Provide feedback on PPA to ARM design teams
- Identify additional physical IP requirements for optimal PPA
- Accelerate adoption of next-generation process and associated flows
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