Arm Applies Cadence Cerebrus to Optimize PPA of Next-Gen 3nm Core Implementation
The world’s insatiable demand for data and its processing is leading to more innovations in the cloud and server infrastructure space. High-performance computing (HPC) and hyperscale customers demand improved cloud workload performance from CPUs without affecting the power and area. The industry needs efficient data center servers that deliver the maximum performance for today’s complex workloads.
Arm is a leader in CPU IP for server and infrastructure SoCs. Optimizing the power, performance, and area (PPA) of an Arm-based SoC has become challenging with the growing complexity of advanced nodes. Cadence collaborates with Arm and enables mutual customers to overcome these challenges and reduce their time to market. As part of that collaboration, Arm leveraged the Cadence Cerebrus Intelligent Chip Explorer to push the performance of their latest Neoverse V2 core with reduced effort and a fast time to results.
During CadenceLIVE Silicon Valley 2022, Arm mentioned the resulting improvements of enabling the Cadence Cerebrus solution in the existing Arm implementation flow. Starting from a mature baseline, this integration enabled Arm to improve PPA (38% reduction in leakage power, 1.7% improvements in utilization, and 3.2% improvement in total negative slack) as well as team productivity.
How Does Cadence Support Arm Neoverse V2-Based SoCs?
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