Arm Virtual Platform co-simulation solution accelerates SoC verification
Virtual platform co-simulation is an advanced technique for accelerating SoC verification. The advantages are substantial and include earlier validation of hardware and software design assumptions, faster iteration of hardware and software changes and more efficient co-debug compared. Arm Fast Models have long been the golden reference models for the Arm architecture and these high-fidelity models make the ideal companion for co-simulation scenarios. In this blog we highlight the advantages of Avery Design Systems’ integration between Fast Models, Avery verification IP and the device under test. We’ll show how this integrated solution provides customers with an efficient and scalable SoC verification environment.
Through close collaboration with Arm, Avery Design Systems offers a virtual platform co-simulation solution for all Arm processors. The Avery solution provides complete hardware virtual platform to verify implementation of Arm-based designers earlier and comprehensively. Avery’s virtual platform co-simulation solution for Arm Fast Models supports connecting various Arm processors and virtual platform subsystems to SoC hardware captured at the Register Transfer Level to enable complete hardware and software system simulation. Key features added to the virtual platform include making it easier to perform hardware and software debug in a coordinated way. Users can run and control the execution of the hardware simulation and the software running on Arm Fast Models. By synchronizing the two environments and having effective hardware and software co-debug controls users can now see the complete state of the design. Visibility includes runtime memory or memory mapped registers in the software that are part of the SoC as well as hardware registers that reflect the current design status accessible with the debugger.
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