Accelerating RISC-V Processor Verification: A Co-Simulation Strategy

By _Frontgrade Gaisler Blog

September 17, 2024

With RISC-V processor architectures gaining traction across diverse computing systems, ensuring their reliability through rigorous verification becomes more crucial than ever. We have embraced a robust co-simulation strategy for verifying the NOEL-V RISC-V processor. This strategy integrates behavioural simulation with the SPIKE open-source RISC-V ISA simulator.

The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The NOEL-V is designed for space applications, targeting high-performance and fault-tolerance. The processor model offers many customization options and its advanced design required advanced verification strategies.

The Challenge of Processor Verification

Traditional processor verification methodologies often rely on a combination of simulation, formal methods, and emulation. Simulation-based approaches entail executing test vectors on a model of the processor to validate its behavior against the expected outcomes. While effective, simulation is time-consuming and may not capture all corner cases. Formal methods, on the other hand, provide mathematical proofs of correctness but are often limited in scalability and practicality. Emulation offers a middle ground, but it is costly and complex to set up.

The RISC-V ecosystem’s flexibility allows us to tailor verification approaches to better suit various implementations and configurations.

Our Approach: Comparative Analysis with SPIKE

Our verification strategy for the NOEL-V processor revolves around comparing execution flows between two models: the behavioural simulation of NOEL-V’s VHDL implementation and the SPIKE RISC-V ISA simulator.

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