Improving RISC-V Processor Quality with Verification Standards and Advanced Methodologies
At the RISC-V Summit in December, there were presentations halfway between a keynote and a technical session. known as RISC-V Spotlights. These were presented to the entire group of attendees but were not blessed with the keynote title. Maybe this is like the way that when a physician in Britain becomes a surgeon, they drop the title "Dr." and go back to "Mr.". A spotlight is even better than a keynote. One spotlight was by Simon Davidmann of Imperas titled Improving RISC-V Processor Quality with Verification Standards and Advanced Verification Methodologies.
Simon and I go back a long way, ever since he was the VP of Sales for Ambit in Europe in the era when I was VP of Engineering. One of our lead customers was Ericsson in Stockholm, and I remember jointly visiting the group there at least once. Ericsson was what I thought of as a dream customer, at least partially because everyone knows who they are. They were also a dream customer in another way: their design was too big for any other synthesis tool to handle, but our BuildGates product could just synthesize the entire design. When that happens to a customer, they pretty much would just say, "please take our money," and Ericsson did. But I digress.
Related Semiconductor IP
- 32 Bit - Embedded RISC-V Processor Core
- ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
- ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
Related Blogs
- Raising RISC-V processor quality with formal verification
- Effectively hiding sensitive data with RISC-V Zk and custom instructions
- Integrating Coherent RISC-V SoCs: Advanced Solutions with Perspec
- Reducing Manual Effort and Achieving Better Chip Verification Coverage with AI and Formal Techniques
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?